1. Field of the Invention
The present invention relates to an isolation region fabrication process in a semiconductor device. More particularly, the present invention relates to a fabrication process in a semiconductor memory device for simplifying the process for forming an isolation region.
2. Description of the Related Art
In recent years, as research and fabrication techniques of semiconductor devices continues and the fields of application of memory devices expands, memory devices having large storage capacities are being developed. A need for memory cell miniaturization has promoted the development of high density memory devices at an increasingly rapid rate. Semiconductor design strategies to double integration of on-chip memory components continues to expand with each new generation.
A particularly significant factor in the recent achievements towards miniaturization and high integration of memory devices is a reduction of the isolation region separating adjoining memory cells,
Several isolation techniques are particularly well-known including: LOCOS (LOCal Oxidation of Silicon), a method for selectively growing a thick oxide film on a semiconductor substrate and using it as the isolation region; SWAMI (Side Wall Masked Isolation), a method for preventing the extension of an oxide film from an isolation region to a device-forming region during field oxidation, by etching a semiconductor substrate in the isolation region to form either a nitride film or mask on previously etched side walls; SEPOX (SElective Polysilicon OXidation), a method for oxidizing polycrystalline silicon film and using it as the isolation region; and BOX (Buried Oxide Isolation), a method for burying an insulating material by first forming a groove.
FIGS. 1A to 1F are a step-by-step illustration of a process for forming an isolation region based on the conventional SWAMI technique discussed above.
FIG. 1A shows an isolation region which is first formed with opening OP, first oxide film OX1, also known as buffer oxide film, and first nitride film N1 sequentially deposited on first conductive type semiconductor substrate 100. Semiconductor substrate 100 is then exposed by removing portions of first nitride film N1 and first oxide film OX1 corresponding to an isolation region. This is accomplished by a dry etching process. The thin opening OP having inclined side surfaces is subsequently formed as shown in FIG. 1A. The inclined side surfaces are formed by wet etching exposed semiconductor substrate 100.
As shown in FIG. 1B, second oxide film OX2 is then formed, serving as a buffer. Second nitride film N2 and third oxide film OX3 serve as spacers and are deposited sequentially over the resultant structure.
FIG. 1C shows spacers subsequently formed by isotropically etching the second oxide film OX2 and the third oxide film OX3 and the second nitride film N2 using a dry etching process. A channel-stop layer 13 is then formed by ion-implanting a first conductive type impurity, such as boron, to prevent field inversion.
In FIG. 1D, the spacer portion of third oxide film OX3 is removed using a wet etching process.
In FIG. 1E, field oxide film 14 is then formed by oxidizing exposed semiconductor substrate 100.
Finally, as shown in FIG. 1F, the isolation process is completed by removing the first nitride film N1 and the second nitride film N2 and the first oxide film OX1.
The above described isolation method based on the conventional SWAMI technique etches the semiconductor substrate corresponding to the isolation region to form spaces along previously etched side walls. This conventional technique works well to reduce the size of the so-called bird's beak. A large bird's beak is a problem commonly associated with the LOCOS semiconductor fabrication technique discussed above.
The spacer forming step of the SWAMI fabrication process, however, is unfavorably complex. Furthermore, because spacers are formed before field oxide film 14 is grown, the surface of the field oxide film 14 is severely uneven, particularly closer to the boundaries between the isolation region and the device-forming region (see FIG. 1F). This unevenness further complicates and adversely affects subsequent surface layering and etching of the semiconductor memory fabrication process.